The present invention relates to methods and structures for addressing ESD and antenna effects experienced by devices in the presence of through-silicon vias.
Finished integrated circuit devices typically include diffusions and implant regions in the body of a silicon wafer. Above the silicon itself is a gate dielectric layer (such as an oxide), and above that a gate layer in which transistor gates are patterned. The gate layer is usually polysilicon, but in some fabrication processes it can be metal. Above that are several layers of metal interconnects, each separated from the previous layer by a dielectric. Where interconnections are required from one layer to another, an opening is formed through the intervening dielectric layer and filled with a conductive material. There are many variations on this structure, but the one just described is common.
The interconnections between layers are referred to as ‘vias’ if they interconnect two metal interconnect layers, or ‘contacts’ if they connect the first metal interconnect layer to the silicon or gate layers. For simplicity of discussion, no distinction is made herein between ‘contacts’ and ‘vias’, and the two terms are used interchangeably herein.
The first metal interconnect layer above the wafer itself is referred to as “metal 1”, or M1 for short. During fabrication, this layer is formed over the underlying dielectric and then patterned to form individual conductors. The next dielectric layer is then formed above M1, vias are opened as required in this layer, and then a Metal 2 (M2) layer is formed and patterned. This process continues on up through M3, M4, and so on to the highest metal layer.
During the process of fabricating an integrated circuit, it often happens that M1 conductors are connected through a contact to the gate poly of a MOSFET. During reactive-ion etching process steps, the M1 conductors pick up charge from the plasma and can build up a high enough voltage relative to the substrate as to break down the thin dielectric that separates the gate poly from the substrate. This destructive phenomenon is known as “plasma induced gate oxide damage”, or more colloquially the “antenna effect”. The antenna effect usually is not a problem after fabrication, because by that time every M1 conductor has at least one driver connected to it. A driver includes a source or drain diffusion or implant, which forms a diode with the larger body of silicon in which it resides. Whether forward or reverse biased, this diode either conducts or non-destructively breaks down, before the voltage on the M1 conductor reaches the magnitude at which the gate dielectric breaks down.
But since conductive paths are often routed in such a way that they jump among different metal layers, the connection of a transistor gate terminal to a driver often is not completed until higher layers of metal are formed on the wafer. There will be a period of time during fabrication, therefore, that M1 conductors are connected to gate poly and nowhere connected to a driver. During these time periods, the gate dielectrics are subject to a risk of breakdown due to charge buildup on the M1 conductor to which it is connected.
There is a related source of plasma induced gate oxide damage which occurs during fabrication, referred to herein as “antenna effect electrostatic discharge (ESD) damage.” This problem occurs because during fabrication some M1 conductors are connected through contacts to the drain diffusion or implant of N-channel transistors, thereby providing another path for charge built up on the conductors to break down gate dielectrics as it couples to the gate poly.
Both of the above phenomena occur during fabrication, and arise because the conductors pick up charge from the etching plasma or from other sources. They are to be distinguished from a third source of charge-induced gate dielectric damage, referred to herein as “external ESD”. External ESD occurs from exposure to an external source of static discharge like a human touch. External ESD usually occurs after fabrication, during handling of completed devices. The problem of external ESD is addressed by including large ESD protection circuits on the chip and connecting them to all the I/O pads.
At least three different solutions have been used to address the problem of destructive charge buildup during fabrication. In one solution, the routing of the circuit is changed so that only a small segment of M1 is directly connected to the gate and the balance of the net is routed through higher levels of metal. The length of M1 material connected to gate poly is then extremely short during the fabrication process, and does not become long until a higher layer of metal is formed which also makes the final connection to a driver. Since the ability of a conductor to pick up deleterious charge from the etching plasma is greatly reduced when the length of the conductor is small, the risk of antenna effect gate dielectric damage is minimized by this technique. On the other hand, this solution places a heavy burden on routing software.
A second solution is similar to the first in that transistor gates are connected directly to the highest layer of metal. It differs in that another via nearby each gate is provided as well to connect back down to M1 where more standard routing can take place. Like the first solution the conductor length in M1 connected to the gate is extremely short until the highest layer of metal is applied, which is the same step in which the final connection is made to a driver. But the impact on routing software is minimized since nearly the entire length of each interconnect that would take place in M1 absent antenna considerations, remains in M1. On the other hand, the requirement for two vias for every gate undesirably occupies valuable chip area.
In yet a third solution, extra diodes (called “antenna diodes”) are formed adjacent each input and connected to the transistor gates in the M1 level. The diodes are formed by implanting an N+ region in P− substrate or a P+ region in an N-substrate, for example. These diodes are reverse biased during normal circuit operation, but during fabrication they will protect the gate dielectrics by breaking down non-destructively before the voltage on the M1 conductor reaches the magnitude at which the gate dielectrics break down. Antenna diodes are typically placed close to the transistor gates which they protect. On some chips the antenna diodes are added near only those transistors that are at risk for antenna effect damage, for example near only those transistors to which a long M1 conductor is connected that does not also connect in M1 to a driver. On other chips they are added near every transistor. Since one diode can protect more than one transistor if they are all nearby and have interconnected gates, it is typical that only one antenna diode is provided for each input of a cell. For example, in a CMOS inverter cell, only one antenna diode will be provided for protecting the gate dielectrics of both the N-channel and P-channel transistors. Often two entire libraries of cells are provided, one which includes an antenna diode for each input, and one which includes no antenna diodes. For a particular design, the chip designer typically chooses to use one library or the other in its entirety throughout the design, thereby in effect choosing for the entire design whether to include or not include antenna diodes throughout.
In yet a fourth solution, the router “drops in” antenna diodes in long routes.
The use of antenna diodes as in the third and fourth solutions above, can avoid the problems of the first and second solutions, but they undesirably occupy valuable chip area. They can also increase the capacitance experienced at the cell inputs. When used, therefore, these diodes are typically kept as small as permitted (in terms of chip area occupied) given the fabrication process. In particular, in plan view, the M1 contact area for the diode cathode is equal to the minimum contact size permitted by the fabrication process, and the N+ region below it has an area equal to the minimum required by the fabrication process to enclose the minimum contact area. As an example, the contact might be 0.18 microns square, and the N+ region might be 0.38 microns square, allowing a 0.1 micron margin on all four sides of the contact.
ESD protection circuits, provided on I/O pads to protect against external ESD events, also usually incorporate diodes. These diodes however are much larger than antenna diodes, since they are designed to dissipate much larger and much more sudden charge buildups. They should not be confused with antenna diodes, which are designed more to bleed off lower levels of charge accumulating more gradually.
Separately, as integrated circuit scaling becomes increasingly difficult with each technology node, three-dimensional (3D) integration technologies have emerged as viable alternatives to achieve the requisite integration densities. 3D integration improves system performance and allows heterogeneous integration of circuit blocks. Many 3D integration techniques include vertical interconnects using through-silicon vias (TSVs). A TSV is a via that passes through the entire body of the chip connecting M1 on the top surface of the chip to a metal connection on the bottom surface of the chip. TSVs have very high aspect ratios, and therefore exhibit many of the same risks of charge accumulation during fabrication that M1 conductors exhibit during fabrication. The problem can actually be worse for TSVs, because many of them are intended to connect to contacts on the next stacked chip without the standard ESD protection afforded by an intervening I/O structure. Those TSVs which are connected on the chip to gate poly therefore will not be connected to a driver until stacking, thereby exposing the gate dielectric to damage both from charge pickup throughout the entire process of fabricating the chip, as well as from external ESD events during post-fabrication handling.
One solution that has been proposed for TSVs is the formation of a temporary layer of metal covering the entire underside of the wafer, formed as the last step of wafer fabrication. Such a metallization shorts together all the TSVs, thereby widely distributing any charge picked up during post-fabrication handling and before the chip is stacked. The connections between the TSVs and the back-side metallization are then removed before final assembly of the stack. However, TSVs are typically formed relatively early in the chip fabrication process, prior to the M1 layer. Since the back-side metallization is not applied until the last step of wafer fabrication, it does not protect gate dielectrics from charge accumulation during all the etching steps that occur during the patterning of all the layers from M1 up. Other than this solution, antenna diodes can be used as described above, but at the cost of chip area as described above.